1. Field of the Invention
The present invention relates to a power amplifier linearization method and apparatus, and more particularly, to a method and apparatus for effectively linearizing a power amplifier having a plurality of distortion generating sources.
2. Description of the Related Art
Recently, a power amplifier in a mobile communication system has been required to amplify a signal with high efficiency and high linear characteristics. In addition, a next generation mobile communication system uses a complicated modulation scheme in order to transmit a large amount of data to the user in a short time.
Accordingly, the peak-to-average power ratio (PAPR) of the signal increases. Generally, in order to provide linear amplification, a power amplifier operates at a back off point equal to or greater than the peak-to-average power ratio of a signal.
However, at this point, the power amplifier exhibits a considerably low efficiency characteristic. This is because the stable operation of a transmitter is not ensured due to an increase of the heating value of the transmitter. Therefore, an additional cooling system is required.
In order to improve the efficiency of a power amplifier at a back-off point, a Doherty amplifier has recently received wide attention.
FIG. 1 is a block diagram illustrating the configuration of a conventional Doherty power amplifier.
Referring to FIG. 1, a Doherty amplifier 100 includes: a power divider 102; an input phase compensation unit 104; a carrier amplifier 106; a peaking amplifier 108; offset lines 110 and 112 configured to generate a high peaking output impedance when the peaking amplifier does not operate, and thus to allow the occurrence of a suitable load modulation phenomenon of the carrier amplifier; and a combiner 114.
The power divider 102 divides and outputs an input signal to the carrier amplifier 106 and the peaking amplifier 108. The carrier amplifier 106 uses relatively high input Direct Current (hereinafter, referred to as “DC”) bias. The peaking amplifier 108 uses relatively low input DC bias. Each of the carrier amplifier 106 and peaking amplifier 108 amplifies the input signal according to a preset amplification gain and outputs the amplified input signal to the combiner 114. The combiner 114 combines the output signal of the carrier amplifier 110 and the output signal of the peaking amplifier 115. The input phase compensation unit 104 compensates for a phase difference which is caused by the offset lines 110 and 112 and the combiner 114.
FIG. 2a is a graph illustrating the fundamental current components of the carrier amplifier 106 and peaking amplifier 108 in ideal and real cases.
Referring to FIG. 2a, in the ideal case, it can be understood that the fundamental current components of the carrier amplifier 106 and peaking amplifier 108 have constant slopes according to the increase of an input voltage. However, in the real case, the carrier amplifier 106 and peaking amplifier 108 may be configured with a field effect transistor (FET), a high electron mobility transistor (HEMT), a bipolar junction transistor (BJT) or the like, which are semiconductor elements, wherein the current components of the FET, HEMT, and BJT increase in a square fashion or exponential fashion. When the current feature is applied to the peaking amplifier 108, the fundamental current components of the peaking amplifier 108 are the same as the real current feature in FIG. 2a. 
FIG. 2b is a graph illustrating fundamental voltage components of the carrier amplifier 106 and peaking amplifier 108 in ideal and real cases.
Referring to FIG. 2b, it can be identified that the fundamental voltage components of the carrier amplifier 106 and peaking amplifier 108 in the real case are the same as in the ideal case. The fundamental voltage components are determined by the fundamental current components, the output matching impedance of the carrier amplifier 106 and the output matching impedance of the peaking amplifier 108, wherein the output matching impedances are as Equation 1 below:
                              Z          C                =                  {                                                                                                                                        Z                        T                        2                                                                    Z                        L                                                                                                                        0                      ≤                                              V                        in                                            <                                              0.5                        ·                                                  V                                                      in                            ,                            Max                                                                                                                                                                                                                                  Z                        T                        2                                                                                              Z                          L                                                ·                                                  [                                                      1                            +                                                                                          I                                P                                                                                            I                                C                                ′                                                                                                              ]                                                                                                                                                                        0.5                        ·                                                  V                                                      in                            ,                            Max                                                                                              ≤                                              V                        in                                            ≤                                              V                                                  in                          ,                          Max                                                                                                                                ⁢                                                          ⁢                              Z                P                                      =                          {                                                                                                                  ∞                                                                                              0                          ≤                                                      V                            in                                                    <                                                      0.5                            ·                                                          V                                                              in                                ,                                Max                                                                                                                                                                                                                                                                              Z                            L                                                    ·                                                      [                                                          1                              +                                                                                                I                                  C                                  ′                                                                                                  I                                  P                                                                                                                      ]                                                                                                                                                                            0.5                            ·                                                          V                                                              in                                ,                                Max                                                                                                              ≤                                                      V                            in                                                    ≤                                                      V                                                          in                              ,                              Max                                                                                                                                                            ⁢                                                                          ⁢                                      I                    C                    ′                                                  =                                                                            I                      C                                        ·                                                                  Z                        T                                                                    Z                        L                                                                              -                                                            I                      P                                        .                                                                                                          (        1        )            
In Equation 1, Vin represents an input voltage, ZC represents the output matching impedance of the carrier amplifier 106, ZP represents the output matching impedance of the peaking amplifier 108, ZL represents a matching impedance at a point where the power of the carrier amplifier 106 and the power of the peaking amplifier 108 are combined, and ZT represents the characteristic impedance of the quarter wave transmission line between the carrier amplifier 106 and the peaking amplifier 108 in the combiner 114. Generally, there is a relation of ZL=ZT/2. In addition, IC represents input current of the carrier amplifier 106, and IP represents input current of the peaking amplifier 108.
Referring to Equation 1, it can be identified that, although the fundamental current components of the peaking amplifier 108 in the real case are less than those in the ideal case, the fundamental voltage components in the real case are the same as those in the ideal case, as shown in FIG. 2b, because the amplitudes of the ZC and ZP increase.
FIG. 3 is a graph illustrating the input/output power of the Doherty amplifier 100 in the ideal and real cases.
Referring to FIG. 3, in the ideal case, the Doherty amplifier 100 has a linear relation between the input and output power. However, in the real case, since the fundamental current components of the peaking amplifier 108 decrease as shown in FIG. 2a, the Doherty amplifier 100 has an output power lower that in the ideal case, so that the output power of the Doherty amplifier 100 including the peaking amplifier 108 cannot have a linear relation, and thus has an undesired distortion characteristic.
FIG. 4 is a graph illustrating a memory effect in a real Doherty amplifier.
The memory effect means that the distortion component of an amplifier is influenced by not only the current input signal, but also by previous input signals. The memory effect in an amplifier can be identified through a non-linearity measurement using a two-tone signal. When applying a two-tone signal to an amplifier, and observing the fundamental wave components of the amplifier and a third-order distortion signal with respect to the same output power, it is possible to identify third-order distortion signals having different amplitudes and different phases depending on the bandwidths of two-tone signals. Through such a method, it is possible to measure a memory effect. Generally, a large memory effect occurs in an intermediate output power, while a large memory effect is not observed in a low output power because a distortion component caused by the amplifier itself is small in the low output power. In addition, in a high output power, since the distortion component caused by the power amplifier itself is large, it is impossible to recognize a memory effect.
Referring to FIG. 4, it can be understood that the Doherty amplifier shows a memory effect characteristic different from that of a general amplifier. This is because the Doherty amplifier is configured with a carrier amplifier and a peaking amplifier, and the carrier amplifier and peaking amplifier operate differently from each other and thus show mutually different distortion characteristics.
As described above, not only the Doherty amplifier but also the other power amplifiers generate a non-linear component to distort an output signal, thereby degrading the signal quality. Therefore, in order to satisfy the linearity required in communication systems, it is necessary to develop a separate linearization technique. Among linearization techniques, a digital predistorter processes signals in a digital band, and thus has an excellent economical efficiency and expansion possibility, as compared with the other linearization techniques.
FIG. 5 is a block diagram illustrating the configuration of a Doherty amplification system including a digital predistorter, to which the present invention is applied.
Referring to FIG. 5, a Doherty amplification system includes a Doherty amplifier 100, a digital predistorter 200, a digital predistorter controller 300, a digital-to-analog converter (DAC) 400, an analog-to-digital converter (ADC) 500, an up converter 600, and a down converter 700.
The operation of the Doherty amplification system illustrated in FIG. 5 is as follows.
At an initial operation, the digital predistorter 200 enters an initial mode.
The initial mode means an operation mode for measuring the non-linear characteristic and memory effect of the Doherty amplifier 100. In the initial mode, it is possible to use either a specified signal which makes it possible to identify the characteristics of the Doherty amplifier 100 in the entire operation region thereof, or a signal used in a real communication system during a predetermined time period. Signals used in the initial mode will be inclusively designated as a test signal.
First, a digital signal, which is a test signal, is inputted to the digital predistorter 200 and the digital predistorter controller 300. However, in the initial mode, the signal inputted to the digital predistorter 200 passes through the digital predistorter 200 without any predistortion. The signal which has passed through the digital predistorter 200 is converted into an analog signal through the DAC 400. The analog signal which has passed through the DAC 400 is inputted to the up converter 600 and is thus converted into a high-frequency analog signal. The high-frequency analog signal is inputted to the Doherty amplifier 100 and is amplified therein. The analog signal which has been amplified by the Doherty amplifier 100 is distorted and thus has a non-linear characteristic and a memory effect. Most of the signal which has been amplified by the Doherty amplifier 100 propagates over the air, and a part thereof is converted into a low-frequency signal by the down converter 700. The low-frequency analog signal which has passed through the down converter 700 is converted into a digital signal through the ADC 500. The digital signal which has passed through the ADC 500 is inputted to the digital predistorter controller 300.
The digital predistorter controller 300 compares the test signal with a signal distorted by the Doherty amplifier 100, and perceives a non-linear characteristic and a memory effect which are caused by the Doherty amplifier 100. Using the perceived information, the digital predistorter controller 300 calculates a configuration value of the digital predistorter 200 in order to compensate for the non-linear characteristic and memory effect caused by the Doherty amplifier 100.
For reference, for convenience of description of the present invention, the non-linear characteristic represents an amplitude modulation-to-amplitude modulation (AM-to-AM) characteristic in which the amplitude of an output signal varies non-linearly depending on the amplitude of an input signal, and an amplitude modulation-to-phase modulation (AM-to-PM) characteristic in which the phase of an output signal varies non-linearly depending on the amplitude of an input signal. The digital predistorter 200 is configured with a look-up table (LUT), a polynomial, or the like.
Therefore, the digital predistorter controller 300 provides an LUT configuration value or a coefficient of a polynomial of the digital predistorter 200.
FIG. 6 is a block diagram illustrating the inner configuration of the conventional digital predistorter 200.
Referring to FIG. 6, the conventional digital predistorter is configured with an amplifier compensator 210.
The amplifier compensator 210 compensates for only the non-linear characteristic of the Doherty amplifier 100, or compensates for both non-linear characteristic and memory effect. In addition, a signal which has passed through the amplifier compensator 210 is inputted to the DAC 400 shown in FIG. 5.
The amplifier compensator 210 may be configured with a polynomial, may be configured with an LUT, and may be configured with both polynomial and LUT. In addition, Volterra Series, a reduction model of Volterra Series, a Wiener model, an expansion model of the Wiener model, a Hammerstein model, an expansion model of the Hammerstein, etc. may be applied to the amplifier compensator 210.
Generally, if an amplifier has a plurality of distortion generating sources to be linearized, and the respective distortion generating sources generate the same non-linear characteristic and memory effect, the non-linear characteristic and memory effect can be sufficiently compensated through the amplifier compensator 210 shown in FIG. 6.
However, in the case of an amplifier, such as a Doherty amplifier, which includes distortion generating sources generating mutually different non-linear characteristics and memory effects, there is a limitation in a degree of linearization improvement when linearization according to the conventional linearization manner is performed as in the amplifier compensator 210.